This program is an effective step to improve the scientific level and information of computer scientists, programmers and craftsmen in the field of computer and electronics.

In this program, an attempt has been made to provide general information on vhdl in a simple project.

In this program, you will be able to program a project in a powerful Modelsim and Active-VHDL application environment.

History :

The VHDL language was originally intended to simulate, model, and understand more of the regional contexts in which the synthesis or synthesis of researchers as an automatic process of design redesign was added. The VHDL language in North America, as well as in Europe, is used by 8% of system engineers, which is still growing. VHDL has no limitations for the user in terms of the uniqueness of the type of description. In fact, I can use a program both behaviorally and textually, ie mentioning all available gates. It is small so that a complete system can be designed with it. One of the reasons for the increase in the popularity of this language is the existence of a number of simulation software with a reasonable price, such as Active VHDL. Although VHDL mostly focuses on electronics, it is actually known as a global modeling language and for modeling and simulation. Electro-mechanical, hydraulic, chemical, etc. systems are used.